1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same.
2. Description of the Related Art
A process of manufacturing a semiconductor device comprises a step of forming plural conductive layers on a semiconductor substrate and a step of forming contact holes reaching respective conductive layers for connection of wires to the conductive layers (see JP-A 2002-184860). For example, when a MOSFET is formed on the semiconductor substrate, source/drain-diffused regions are formed in the semiconductor substrate, and a gate electrode is formed on the semiconductor substrate with a gate insulator sandwiched therebetween. Subsequently, an interlayer insulator is formed covering these diffused regions and the gate electrode. Then, a resist pattern formed on the interlayer insulator is employed as a mask to carry out a process of RIE (Reactive Ion Etching) to form contact holes through: the interlayer insulator. A wire material is buried in the contact holes to form contacts for wiring.
In this case, the contact hole reaching the gate electrode has a different depth from that of the contact holes reaching the diffused regions located deeper than the gate electrode. Therefore, when these contact holes are formed at the same time, the contact hole for the gate electrode located shallower is opened first. As a result, the gate electrode suffers damage from RIE until the contact holes reaching the source/drain-diffused regions are opened. At that time, attachment of foreign substrates to the surface of the gate electrode wire on the bottom of the contact hole tends to result in a contact interface with a high electrical resistance. When the width of the bottom of the contact hole is broadened to form a reverse-tapered hole, a void (cavity) may be formed in the wire material buried later in the contact hole, causing a connection failure in the contact hole possibly.